module line(/*AUTOARG*/
   // Outputs
   read_data1, read_data2, read_data3, read_data4,
   // Inputs
   clk, reset, w_data1, w_data2, wr1, wr2, wen1, wen2, ren1, ren2,
   ren3, ren4
   );

input clk;
input reset;
input [31:0] w_data1;
input [31:0] w_data2;
input wr1;
input wr2;
input wen1;
input wen2;
input ren1;
input ren2;
input ren3;
input ren4;
output [31:0] read_data1;
output [31:0] read_data2;
output [31:0] read_data3;
output [31:0] read_data4;


dflop bit31 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[31]),
.w_data2(w_data2[31]),
.read_data1(read_data1[31]),
.read_data2(read_data2[31]),
.read_data3(read_data3[31]),
.read_data4(read_data4[31]));


dflop bit30 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[30]),
.w_data2(w_data2[30]),
.read_data1(read_data1[30]),
.read_data2(read_data2[30]),
.read_data3(read_data3[30]),
.read_data4(read_data4[30]));


dflop bit29 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[29]),
.w_data2(w_data2[29]),
.read_data1(read_data1[29]),
.read_data2(read_data2[29]),
.read_data3(read_data3[29]),
.read_data4(read_data4[29]));


dflop bit28 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[28]),
.w_data2(w_data2[28]),
.read_data1(read_data1[28]),
.read_data2(read_data2[28]),
.read_data3(read_data3[28]),
.read_data4(read_data4[28]));


dflop bit27 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[27]),
.w_data2(w_data2[27]),
.read_data1(read_data1[27]),
.read_data2(read_data2[27]),
.read_data3(read_data3[27]),
.read_data4(read_data4[27]));


dflop bit26 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
.ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[26]),
.w_data2(w_data2[26]),
.read_data1(read_data1[26]),
.read_data2(read_data2[26]),
.read_data3(read_data3[26]),
.read_data4(read_data4[26]));


dflop bit25 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
.ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[25]),
.w_data2(w_data2[25]),
.read_data1(read_data1[25]),
.read_data2(read_data2[25]),
.read_data3(read_data3[25]),
.read_data4(read_data4[25]));


dflop bit24 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[24]),
.w_data2(w_data2[24]),
.read_data1(read_data1[24]),
.read_data2(read_data2[24]),
.read_data3(read_data3[24]),
.read_data4(read_data4[24]));


dflop bit23 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[23]),
.w_data2(w_data2[23]),
.read_data1(read_data1[23]),
.read_data2(read_data2[23]),
.read_data3(read_data3[23]),
.read_data4(read_data4[23]));


dflop bit22 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[22]),
.w_data2(w_data2[22]),
.read_data1(read_data1[22]),
.read_data2(read_data2[22]),
.read_data3(read_data3[22]),
.read_data4(read_data4[22]));


dflop bit21 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[21]),
.w_data2(w_data2[21]),
.read_data1(read_data1[21]),
.read_data2(read_data2[21]),
.read_data3(read_data3[21]),
.read_data4(read_data4[21]));


dflop bit20 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[20]),
.w_data2(w_data2[20]),
.read_data1(read_data1[20]),
.read_data2(read_data2[20]),
.read_data3(read_data3[20]),
.read_data4(read_data4[20]));


dflop bit19 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[19]),
.w_data2(w_data2[19]),
.read_data1(read_data1[19]),
.read_data2(read_data2[19]),
.read_data3(read_data3[19]),
.read_data4(read_data4[19]));


dflop bit18 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[18]),
.w_data2(w_data2[18]),
.read_data1(read_data1[18]),
.read_data2(read_data2[18]),
.read_data3(read_data3[18]),
.read_data4(read_data4[18]));


dflop bit17 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[17]),
.w_data2(w_data2[17]),
.read_data1(read_data1[17]),
.read_data2(read_data2[17]),
.read_data3(read_data3[17]),
.read_data4(read_data4[17]));


dflop bit16 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[16]),
.w_data2(w_data2[16]),
.read_data1(read_data1[16]),
.read_data2(read_data2[16]),
.read_data3(read_data3[16]),
.read_data4(read_data4[16]));


dflop bit15 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[15]),
.w_data2(w_data2[15]),
.read_data1(read_data1[15]),
.read_data2(read_data2[15]),
.read_data3(read_data3[15]),
.read_data4(read_data4[15]));


dflop bit14 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[14]),
.w_data2(w_data2[14]),
.read_data1(read_data1[14]),
.read_data2(read_data2[14]),
.read_data3(read_data3[14]),
.read_data4(read_data4[14]));


dflop bit13 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[13]),
.w_data2(w_data2[13]),
.read_data1(read_data1[13]),
.read_data2(read_data2[13]),
.read_data3(read_data3[13]),
.read_data4(read_data4[13]));


dflop bit12 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[12]),
.w_data2(w_data2[12]),
.read_data1(read_data1[12]),
.read_data2(read_data2[12]),
.read_data3(read_data3[12]),
.read_data4(read_data4[12]));


dflop bit11 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[11]),
.w_data2(w_data2[11]),
.read_data1(read_data1[11]),
.read_data2(read_data2[11]),
.read_data3(read_data3[11]),
.read_data4(read_data4[11]));


dflop bit10 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[10]),
.w_data2(w_data2[10]),
.read_data1(read_data1[10]),
.read_data2(read_data2[10]),
.read_data3(read_data3[10]),
.read_data4(read_data4[10]));


dflop bit9 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[9]),
.w_data2(w_data2[9]),
.read_data1(read_data1[9]),
.read_data2(read_data2[9]),
.read_data3(read_data3[9]),
.read_data4(read_data4[9]));


dflop bit8 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[8]),
.w_data2(w_data2[8]),
.read_data1(read_data1[8]),
.read_data2(read_data2[8]),
.read_data3(read_data3[8]),
.read_data4(read_data4[8]));


dflop bit7 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[7]),
.w_data2(w_data2[7]),
.read_data1(read_data1[7]),
.read_data2(read_data2[7]),
.read_data3(read_data3[7]),
.read_data4(read_data4[7]));


dflop bit6 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[6]),
.w_data2(w_data2[6]),
.read_data1(read_data1[6]),
.read_data2(read_data2[6]),
.read_data3(read_data3[6]),
.read_data4(read_data4[6]));


dflop bit5 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[5]),
.w_data2(w_data2[5]),
.read_data1(read_data1[5]),
.read_data2(read_data2[5]),
.read_data3(read_data3[5]),
.read_data4(read_data4[5]));


dflop bit4 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[4]),
.w_data2(w_data2[4]),
.read_data1(read_data1[4]),
.read_data2(read_data2[4]),
.read_data3(read_data3[4]),
.read_data4(read_data4[4]));


dflop bit3 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[3]),
.w_data2(w_data2[3]),
.read_data1(read_data1[3]),
.read_data2(read_data2[3]),
.read_data3(read_data3[3]),
.read_data4(read_data4[3]));


dflop bit2 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[2]),
.w_data2(w_data2[2]),
.read_data1(read_data1[2]),
.read_data2(read_data2[2]),
.read_data3(read_data3[2]),
.read_data4(read_data4[2]));


dflop bit1 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[1]),
.w_data2(w_data2[1]),
.read_data1(read_data1[1]),
.read_data2(read_data2[1]),
.read_data3(read_data3[1]),
.read_data4(read_data4[1]));


dflop bit0 (.clk(clk), .reset(reset),
.wen1(wen1), .wen2(wen2),
 .wr1(wr1), .wr2(wr2),
 .ren1(ren1),
.ren2(ren2),
.ren3(ren3),
.ren4(ren4),
.w_data1(w_data1[0]),
.w_data2(w_data2[0]),
.read_data1(read_data1[0]),
.read_data2(read_data2[0]),
.read_data3(read_data3[0]),
.read_data4(read_data4[0]));

endmodule
